Embodiments of the inventive concept described herein relate to memory systems and, more particularly, to memory systems that utilize memory controllers to perform ZQ global management.
Semiconductor memory devices within memory systems may be connected to a memory controller using transmission lines for transmitting signals such as data, addresses and commands. The signals transmitted through the transmission lines may be reflected at ends of the transmission lines. The reflected signals typically act as noise that degrades the fidelity of the original signals, thereby causing a decrease in signal integrity (SI).
To prevent signal reflections, termination resistors may be connected to the termination node of the transmission line. A termination resistor may serve to match impedance between an inside and an outside of a semiconductor memory device. Termination resistors are commonly used in dynamic random access memory (DRAM), which has a fast operating speed. To prevent signal interference between DRAMs, an on die termination (ODT) technique can be utilized by including termination resistors, which are directly connected on a die of the DRAM. In the case of double data rate 3 synchronous DRAM (DDR3 SRAM), which has a fast operating speed above 1000 MHz, even higher signal integrity and reliability may be required. Thus, when impedance matching is not exactly performed due to a change in termination resistance caused by process, voltage, and temperature (i.e., PVT) variations, it may be difficult to rapidly transmit signals and such signals may become degraded.
A conventional DDR3 SDRAM may utilize a ZQ calibration circuit to secure high signal integrity and stability. When the termination resistance value is precisely calibrated based on a calibration code generated from the ZQ calibration circuit, the impedance matching may be accurately made in the memory system.
As will be understood by those skilled in the art, there are typically two different calibration commands in DDR3 that are used to account for variations in the system environment for temperature, voltage and component drift. The ZQ calibration commands operate to calibrate the DRAM's output drivers and ODT values by typically using a precision 240 ohm (±1%) resistor connected from the DRAM's ZQ pin to ground. However, because a ZQ calibration long (ZQCL) command typically takes 512 clocks to complete, it is often used during power-up initialization and reset. Subsequent ZQCL commands can be issued at any time the DRAM is idle and typically only require 246 clocks. In contrast, a ZQ calibration short (ZQCS) command typically requires 64 clocks to complete, so it is used periodically when the DRAM is idle to perform calibrations to account for minor variations in voltage and temperature. Each ZQCS command can typically correct a minimum of 0.5% impedance error within 64 clocks. Both ZQCL and ZQCS can be initiated at any time and as often as required by the BIOS and memory controller to account for larger changes in the system environment. The ZQCL command is typically used when there is more impedance error correction required than a ZQCS can provide.